The present invention relates to a semiconductor device comprising MISFETs that have good characteristics of threshold voltage (V.sub.th) vs. channel length (L.sub.g), and to a process for manufacturing the same.
In MOS devices, there is a tendency to reduce the channel length with a consequent increase in electric field intensity between the source region and the drain region. Therefore, hot carriers are injected into the gate oxide film to suppress these characteristics, as well as to suppress the V.sub.th vs. L.sub.g characteristics. To prevent these problems, some have proposed reducing the electric field intensity between the source region and the drain region relying upon a lightly doped drain (LDD) construction (see the journal, "Nikkei Electronics, a separate volume "Microdevices"", p. 83).
However, employment of the LDD construction makes it necessary to provide side walls and to carry out ion implantation before and after the formation of the side walls. Therefore, the devices which are produced require more manufacturing steps and higher manufacturing cost compared with the devices that are not of the LDD construction. Still further manufacturing steps will be required when LDD construction is adapted to CMOS devices.
Specifically, when LDD construction is adapted to CMOS devices, ion implantation must be carried out one more time on the p-channel metal oxide semiconductor field-effect transistor (P-MOSFET) and on an n-channel metal oxide semiconductor field-effect transistor (N-MOSFET), respectively. Therefore, the photoresist mask must be formed two more times compared with the conventional devices that are not of LDD construction. Therefore, the process is complicated in addition to the extra step for forming the side walls, and the manufacturing cost becomes expensive. It was further clarified by the inventors that the effective channel length becomes extremely short so as to suppress the V.sub.th -L.sub.g characteristics.